| PART |
Description |
Maker |
| 74VHCT74A 74VHCT74AM 74VHCT74ASJ 74VHCT74 74VHCT74 |
Octal D-type Edge-Triggered Flip-Flops With 3-State Outputs 20-SOIC -40 to 85 AHCT/VHCT SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP14
Dual D-Type Flip-Flop with Preset and Clear AHCT/VHCT/VT SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14
|
Fairchild Semiconductor, Corp.
FAIRCHILD[Fairchild Semiconductor]
|
| 74VHC74MTC 74VHC74MX 74VHC74SJ 74VHC74 74VHC74M 74 |
Dual D-Type Flip-Flop with Preset and Clear
Hex Schmitt-Trigger Inverters 14-TSSOP -40 to 85
Quadruple 2-Line To 1-Line Data Selectors/Multiplexers 16-SOIC -40 to 85 AHC/VHC/H/U/V SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14
Quadruple 2-Line To 1-Line Data Selectors/Multiplexers 16-SOIC -40 to 85 AHC/VHC/H/U/V SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP14
|
FAIRCHILD[Fairchild Semiconductor]
Fairchild Semiconductor Corporation
Fairchild Semiconductor, Corp.
|
| 74ACTQ74 74ACTQ74SC 74ACTQ74SJ 74ACTQ74PC |
Quiet Series Dual D-Type Positive Edge-Triggered Flip-Flop
From old datasheet system
|
FAIRCHILD[Fairchild Semiconductor]
|
| 74AC109SCQR |
AC SERIES, DUAL POSITIVE EDGE TRIGGERED J-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16
|
FAIRCHILD SEMICONDUCTOR CORP
|
| 74AC161MTC 74AC161PC 74AC161SC 74AC161SJ 74AC161 7 |
Synchronous Presettable Binary Counter
Synchronous Up Counter AC SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDSO16
Complete, Dual, 12-Bit Multiplying DAC with 8-Bit Bus Interface ACT SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDSO16
Synchronous Presettable Binary Counter ACT SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDIP16
From old datasheet system
Synchronous Presettable Binary Counter
|
Fairchild Semiconductor, Corp.
FAIRCHILD[Fairchild Semiconductor]
|
| 74AUP1G374GF132 74AUP1G374GW 74AUP1G374GM |
Low-power D-type flip-flop; positive-edge trigger; 3-state; Package: SOT891 (XSON6); Container: Tape reel smd AUP/ULP/V SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO6
|
NXP Semiconductors N.V.
|
| TC4027BF |
4000/14000/40000 SERIES, DUAL POSITIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16
|
|
| T74LS113AD1 T74LS113AC1 T74LS113AM1 T74LS113AB1 |
LS SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP14 CERAMIC, DIP-14
LS SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PQCC20 PLASTIC, LCC-20
LS SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14 MICRO, SO-14
LS SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP14 PLASTIC, DIP-14
|
ST Microelectronics
|
| M27W201-80K6TR M27W201-200NZ6TR M27W201-80NZ6TR M2 |
2 MBIT (256KB X8) LOW VOLTAGE OTP EPROM
Test Spring Probe; Current Rating:3A; Leaded Process Compatible:Yes; Length:0.060"; Peak Reflow Compatible (260 C):No; Tip/Nozzle Style:90 Concave RoHS Compliant: Yes 2兆位56Kb × 8低压紫外线可擦写可编程只读存储器和OTP存储
Triple 3-Input Positive-AND Gates 14-SO 0 to 70
Dual J-K Positive-Edge-Triggered Flip-Flops With Clear And Preset 16-SO 0 to 70
Triple 3-Input Positive-AND Gates 14-PDIP 0 to 70
Triple 3-Input Positive-AND Gates 14-SOIC 0 to 70
Dual J-K Positive-Edge-Triggered Flip-Flops With Clear And Preset 16-SOIC 0 to 70
Dual J-K Positive-Edge-Triggered Flip-Flops With Clear And Preset 16-PDIP 0 to 70
2 Mbit 256Kb x 8 Low Voltage UV EPROM and OTP EPROM
2 MBIT (256KB X8) LOW VOLTAGE OTP EPROM
|
STMicroelectronics N.V.
意法半导
STMICROELECTRONICS[STMicroelectronics]
ST Microelectronics
|
| CD54HC162F3A CD54HC162H/3 |
HC/UH SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP DECADE COUNTER, CDIP16
HC/UH SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP DECADE COUNTER, UUC16
|
HARRIS SEMICONDUCTOR
|
| MC10135 MC10135FN MC10135L MC10135P ON0571 |
Replaced by SN54LS175 : Quadruple D-type Flip-Flops With Clear 16-CFP -55 to 125 10K SERIES, POSITIVE EDGE TRIGGERED JBAR-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP16
Replaced by SN54LS175 : Quadruple D-type Flip-Flops With Clear 16-CDIP -55 to 125 10K SERIES, POSITIVE EDGE TRIGGERED JBAR-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP16
Dual J-K Master-Slave Flip-Flop
PIN ASSIGNMENT
From old datasheet system
|
Motorola Mobility Holdings, Inc.
Motorola, Inc.
ONSEMI[ON Semiconductor]
|
